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Johnny Sim
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A Pipeline CPU implemented using an FPGA

Jan 2013 - April 2013
Solo Project

A Pipeline CPU that takes a set of instructions and executes tasks based off those instructions using the Altera DE2 Board and Verilog Hardware Description Language. I implemented a three stage Harvard architecture in Altera Quartus II and Altera Quartus Simulator.
FinalReport.pdf
FinalPresentation.pdf
GitHub Repository
Completed
- Three Stage Harvard Architecture Pipeline
- Designed a simple x86 based register layout
- Example Instructions including ADD, SUB, AND, OR, JUMP, etc
Copyright © 2015-2016 Johnny Sim
LinkedIn: in/jsim253
Email: Jsim253@gmail.com